HELIOS 
Project Helios  Specification

Here is my proposition about the new project : THE NEW ORIC or HELIOS.

ATTENTION : USES THE FREE WEBPACK ISE SOFTWARE OF XILINX.

The following draw is a simple diagram about HELIOS :

schema1

WITH :

CPU 65C816 10 ... 16 MHz
ROM EPROM FLASH 64 ... 2048 KBytes
RAM DYNAMIC 512 KBytes ... 12 MBytes
MEMORY CONTROLLER / DMA FPGA dynamic ram and DMA
SOUND FPGA stereo : 3 voices + 1 noise
8 voices ADPCM stereo (8-16 bits)
GRAPHICS FPGA first version : compatible ULA
second version : ULA2
futur version : enhanced ULA2
static ram: 512 KBytes - 2 MBytes
RTC Not defined  
I/O FPGA rs232
centronics
ide
floppy
mouse
keyboard
Floating point unit FPGA Not defined
DSP FPGA 16 bits fixed point
ISA BUS 16 bits / 8 MHz
BUS SYSTEM BUS 16 bits / 10 ... 16 MHZ (fct CPU)

This project will use many FPGA. WHY ? Because it's more simply to find FPGA chips and it's more flexible, etc.
Therefore this project will be split on four subprojects :

  1. MEMORY CONTROLLER / DMA : his rule is to refresh the dynamic ram and the read/write.
    And too it manages the dma transfert between RAM, RAM/I-O and I/O-I/O. It give
    the hard compatibility with ORIC ATMOS (ORIC 1 too). And too it manages the ISA BUS.
  2. SOUND : his rule is ... to do and to make noise ! It makes sounds in stereo.
  3. GRAPHICS : his rule is ... to display your imagination. Most seriously, it makes display.
  4. I/O : his rule is to manage the input/output system.

For the other chips (Floating point unit, DSP), it will be design later. The RTC (real-time chips (clock ?)) is a chip from National Semiconductor or an other maker.

 

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