CHIP Memory Controller / DMA 

Project Helios  Specification  Memory Controller / DMA CHIP

The main rule of this chip is to manage

Ram dynamic

This part of the chip manages the refresh of the ram dynamic and their access. Contrary of the static ram, the dynamic ram has need to refresh at time to keep "alive" the information.
The OPENCORES Projects is nice because we found a memory controller whose will help us to design our memory controller.

Rom

see above

DMA

This section manages the transfert with Direct memory transfert. It's useful to optimize the flow between IDE and Memory.

Bus isa

It seems that several person want a bus ISA. It's not difficult because the bus system is an ... enhanced bus ISA (specification)!!
The specification of ISA is here.

Chip select

This section manages to the selection of the different chips (Graphic, Sound, memory controller and I/O)

This part of the subproject must implement the hard compatibility with ORIC ATMOS.
This link will give many information about this part.

Hard compatibility

In fact, each module (RAM DYNAMIC, ROM, DMA, ISA, CHIP SELECT) must manage the hard compatibility. Thus it's not really a part of the memory controller.

LINKS

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